(1) Field of the Invention
The present application relates generally to communication interfaces and, more particularly, to transmission rate control in digital communication interfaces.
(2) Description of the Related Art
Modern high-speed interfaces (including serial and parallel interfaces), which may be implemented as links, suffer from several common pitfalls. As one example, ensuring proper timing of data communications via interfaces can be complex and difficult. Reference clocks are timing sources upon which the timing of data communications (e.g., transmission, conveyance across a link, reception) are based. Ideally, the number of reference clocks would be minimized to reduce the complexity of and space occupied by the reference clock circuitry. However, interface data rates are tightly tied to interface reference clock frequencies, thus making it difficult to consolidate these reference clock sources and driving high the number of discrete reference clock sources on a device/card, especially when multiple interfaces are provided, as different interfaces of the same device may have different throughput requirements. Very specific data rates drive very specific reference clock frequency requirements which are often difficult to satisfy. The fixed reference clock frequencies also do not allow for any flexibility in the system, such as minor data throughput adjustments, feature additions, etc. In a typical serial interface, the following three reference clocks exist: (1) the transmitter reference clock, (2) the transmit link reference clock, and (3) the receiver reference clock.
Existence of multiple interfaces on a device (e.g., an integrated circuit or circuit card) drives number of reference clocks high. This can result in compromised system reliability and increased system complexity and/or cost.
As another example, the separation of the reference clock frequency from the data rate in a typical system today is handled via the use of some form of a backpressure mechanism. Such mechanisms unfortunately have numerous pitfalls. For example, they introduce large response latency as the receiver has to inform the transmitter to slow down and the transmitter has to react to this request. In the meantime the data path between the transmitter and the receiver might be filled with data which the receiver has to be able to accommodate. Also, the large response latency therefore results in large buffering capacity requirement, and thus large buffer (memory) resource consumption. Furthermore, the large buffer resource results in increased data delay and increased data delay variation (i.e., jitter). Moreover, the backpressure messaging itself consumes the precious data path bandwidth.
Reference clock consolidation for interfaces having similar bit rates has been achieved in the past by relying on backpressure control of the interfaces to maintain their respective appropriate rates. With backpressure control, a receiver feeds back an indication to the transmitter to control the rate at which the transmitter transmits data. However, due to latency in receiving and responding to backpressure control signals at interface transmitters, additional storage buffer capacity at interface receivers is required when this technique is used. If the interface rates are substantially dissimilar, using this technique can become impractical because of the large amount of buffer storage required.
For example, substantial latencies result in lengthy round-trip times (Trtt) for a transmitter to receive a backpressure indication pertinent to data it has transmitted. As buffer capacity requirements are a function of the product of the round-trip times and the data rates, market demands for increasing data rates thereby force the use of larger buffer capacities as round-trip times remain fairly constant when flow control is based solely on backpressure.
Thus, a technique is needed that avoids primary reliance on backpressure flow control.
The use of the same reference symbols in different drawings indicates similar or identical items.